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a AD8152 * 34 34, 3.2 gbps asynchronous digital crosspoint switch rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. * patent pending features low cost low power 2.0 w @ 2.5 v (outputs enabled) <100 mw @ 2.5 v (outputs disabled) 34 34, fully differential, nonblocking array 3.2 gbps per port nrz data rate wide power supply range: 2.5 v to 3.3 v lvttl or lvcmos level control inputs: @ 2.5 v to 3.3 v low jitter: 45 ps drives a backplane directly programmable output swing 100 mv to 1.6 v differential 50 on-chip i/o termination user controlled voltage at the load minimizes power dissipation dual rank latches available in 256-ball grid array applications fiber optic network switching high speed serial backplane routing to oc-48 with fec gigabit ethernet digital video (hdtv) data storage networks functional block diagram ou tput l evel dacs outn outp vtto 34 34 di fferential s witch matrix 34 34 mat rix c onnection lat ches c onnection de code ou tput l evel lat ches control logic inn vtti inp d[5:0] a[6:0] re we reset cs update vee vcc AD8152 34 34 general description AD8152 is a member of the xstream line of products and is a breakthrough in digital switching, offering a large switch array (34 34) on very little power, typically 2.0 w. additionally, it operates at data rates up to 3.2 gbps per port, making it suitable for sonet/sdh oc-48 with forward error correction (fec). the AD8152? useful supply voltage range allows the user to operate at lvpecl/cml data levels down to 2.5 v. the control interface is lvttl or lvcmos compatible on 2.5 v to 3.3 v. the AD8152? fully differential signal path reduces jitter and crosstalk while allowing the use of smaller single-ended voltage swings. it is offered in a 256-ball sbga package that operates over the industrial temperature range of 0 c to 85 c. 80ps/div 100mv/div figure 1. eye pattern, 3.2 gbps, prbs 23
rev. a ? AD8152 (@ 25 c, vcc = 2.5 v to 3.3 v, vee = 0 v, r l = 50 , differential output swing = 800 mv p-p, unless otherwise noted.) parameter condition min typ max unit dynamic performance max data rate/channel (nrz) 3.2 gbps channel jitter data rate 3.2 gbps; prbs 2 23 ?1 45 ps p-p rms channel jitter <10 ps propagation delay input to output 660 800 ps propagation delay match 50 120 ps output rise/fall time 20% to 80% 100 ps input characteristics input voltage swing single-ended (see tpc 14) 50 1000 mv p-p input voltage range common-mode (see tpc 15) vee + 0.8 vcc + 0.2 v input bias current 2 m a input capacitance 2pf output characteristics output voltage swing differential (see tpc 18) 100 800 1600 mv p-p output voltage range vcc ?1.2 vcc + 0.2 v output current 2 32 ma output capacitance 2pf termination characteristics resistance 43 50 57 w temperature coefficient 0.05 w / c power supply operating range vcc vee = 0 v 2.25 3.63 v quiescent current vcc all outputs disabled 32 45 ma all outputs enabled 190 ma vee all outputs disabled 32 45 ma all outputs enabled 770 ma t min to t max, all outputs enabled 800 ma logic input characteristics input high (vih) vcc = 3.3 v 2 v input low (vil) vcc = 3.3 v 0.8 v input high (vih) vcc = 2.5 v 1.7 v input low (vil) vcc = 2.5 v 0.7 v logic output characteristics output high (voh) vcc = 3.3 v, ioh = ? ma 2.4 v output low (vol) vcc = 3.3 v, iol = +2 ma 0.4 v output high (voh) vcc = 2.5 v, ioh = ?00 ua 2.1 v output low (vol) vcc = 2.5 v, iol = +100 ua 0.2 v thermal characteristics operating temperature range 0 85 c ja still air 15 c/w 200 lfpm 12 c/w 400 lfpm 11 c/w specifications subject to change without notice. electrical characteristics
rev. a AD8152 ? caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD8152 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1 vcc to vee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 v vtti . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vcc + 0.6 v vtto . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vcc + 0.6 v internal power dissipation 2 AD8152 256-ball sbga (bp) . . . . . . . . . . . . . . . . . . 8.33 w input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . vcc + 0.6 v differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . 1.7 v logic input voltage . . . . . . vee ?0.3 v < v in < vcc + 0.6 v storage temperature range . . . . . . . . . . . . . ?5 c to +125 c lead temperature range . . . . . . . . . . . . . . . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for the device in free air (t a = 25 c): ja = 15 c/w @ still air. maximum power dissipation the maximum power that can be safely dissipated by the AD8152 is limited by the associated rise in junction temperature. the maxi- mum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150 c. temporarily exceeding this limit may cause 16 0 090 10 20 30 40 50 60 70 80 14 8 6 4 2 12 10 ambient temperature ? c maximum power dissipation ?w tj = 150 c 400 lfpm 200 lfpm still air figure 2. maximum power dissipation vs. temperature a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction tem- perature of 175 c for an extended period can result in device failure. to ensure proper operation, it is necessary to observe the maximum power derating curves shown in figure 2. ordering guide model temperature range package description AD8152jbp 0 c to 85 c 256-ball sbga (27 mm 27 mm) AD8152-eval evaluation board
rev. a ? AD8152 ball grid array 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v w y a b c d e f g h j k l m n p r t u v w y 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vee vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vtto vtto vtto vtto vtto vtto vtto vtto vtto vtto vtto vtto vtto vtto vtto vtto vtto vtto vtto vtto vtti vtti vtti vtti vtti vtti vtti vtti vtti vtti vtti vtti vtti vtti vtti vtti o20p o21p o19n o19p o18n o17p o17n o18p o27n o25p o25n o24n o23p o23n o24p o22p o22n o21n o30n o29p o29n o30p o28n o28p o27p o26n o26p o32p o32n o31p o20n o31n o33n o33p o00p o05n o05p o04p o03n o03p o01n o02p o02n o01p o00n o09p o09n o07n o08n o08p o07p o06n o06p o04n o13n o14p o14n o13p o12n o12p o10p o11p o11n o10n o16n o16p o15n o15p i16n i16p i15n i09n i11n i11p i12p i13n i13p i12n i14n i14p i15p i07p i06n i06p i07n i08n i08p i09p i10p i10n i00n i01p i02p i02n i04p i03n i03p i04n i05n i05p i01n i00p i31n i33n i17p i19p i20n i22n i23n i25n i27p i28n i30n i22p i23p i25p i27n i28p i30p i31p i33p i17n i19n i20p i24p i26p i26n i29p i29n i32p i32n i24n i21n i21p i18p i18n d1 reset d2 d3 d0 cs re d5 d4 update a0 we a1 a2 a5 a6 a4 a3 n/c n/c n/c n/c ball diagram, view from the bottom
rev. a AD8152 ? ball mnemonic type description a1 vee power negative supply a2 vee power negative supply a3 vee power negative supply a4 vcc power positive supply a5 vtto power output termination supply a6 out02p i/o high speed output a7 vtto power output termination supply a8 out05p i/o high speed output a9 vtto power output termination supply a10 out08p i/o high speed output a11 vcc power positive supply a12 out11p i/o high speed output a13 vtto power output termination supply a14 out14p i/o high speed output a15 vtto power output termination supply a16 vcc power positive supply a17 vee power negative supply a18 vee power negative supply a19 vee power negative supply a20 vee power negative supply b1 vee power negative supply b2 vee power negative supply b3 vee power negative supply b4 vcc power positive supply b5 vtto power output termination supply b6 out02n i/o high speed output complement b7 vtto power output termination supply b8 out05n i/o high speed output complement b9 vtto power output termination supply b10 out08n i/o high speed output complement b11 vcc power positive supply b12 out11n i/o high speed output complement b13 vtto power output termination supply b14 out14n i/o high speed output complement b15 vtto power output termination supply b16 vcc power positive supply b17 vee power negative supply b18 vee power negative supply b19 vee power negative supply b20 vee power negative supply c1 vee power negative supply c2 vee power negative supply c3 a5 control output address pin (msb) c4 a6 control output address pin (bank des.) c5 out00p i/o high speed output c6 out01n i/o high speed output complement c7 out03p i/o high speed output c8 out04n i/o high speed output complement c9 out06p i/o high speed output c10 out07n i/o high speed output complement c11 out09p i/o high speed output ball mnemonic type description c12 out10n i/o high speed output complement c13 out12p i/o high speed output c14 out13n i/o high speed output complement c15 out15p i/o high speed output c16 out16n i/o high speed output complement c17 d5 control input address pin (msb) c18 d4 control input address pin c19 vee power negative supply c20 vee power negative supply d1 a1 control output address pin d2 a2 control output address pin d3 a3 control output address pin d4 a4 control output address pin d5 out00n i/o high speed output complement d6 out01p i/o high speed output d7 out03n i/o high speed output complement d8 out04p i/o high speed output d9 out06n i/o high speed output complement d10 out07p i/o high speed output d11 out09n i/o high speed output complement d12 out10p i/o high speed output d13 out12n i/o high speed output complement d14 out13p i/o high speed output d15 out15n i/o high speed output complement d16 out16p i/o high speed output d17 d3 control input address pin d18 d2 control input address pin d19 d1 control input address pin d20 d0 control input address pin (lsb) e1 a0 control output address pin (lsb) e2 update control second rank write enable e3 n/c reserved do not c onnect e4 n/c reserved do not c onnect e17 n/c reserved do not c onnect e18 n/c reserved do not c onnect e19 reset control reset/disable outputs e20 cs control chip select enable f1 vcc power positive supply f2 we control first rank write enable f3 in00p i/o high speed input f4 in00n i/o high speed input complement f17 in17n i/o high speed input complement f18 in17p i/o high speed input f19 re control readback enable f20 vcc power positive supply g1 in02p i/o high speed input g2 in02n i/o high speed input complement g3 in01n i/o high speed input complement g4 in01p i/o high speed input g17 in18p i/o high speed input g18 in18n i/o high speed input complement ball grid descriptions
rev. a ? AD8152 ball mnemonic type description g19 in19n i/o high speed input complement g20 in19p i/o high speed input h1 vtti power input termination supply h2 vtti power input termination supply h3 in03p i/o high speed input h4 in03n i/o high speed input complement h17 in20n i/o high speed input complement h18 in20p i/o high speed input h19 vtti power input termination supply h20 vtti power input termination supply j1 in05p i/o high speed input j2 in05n i/o high speed input complement j3 in04n i/o high speed input complement j4 in04p i/o high speed input j17 in21p i/o high speed input j18 in21n i/o high speed input complement j19 in22n i/o high speed input complement j20 in22p i/o high speed input k1 vtti power input termination supply k2 vtti power input termination supply k3 in06p i/o high speed input complement k4 in06n i/o high speed input k17 in23n i/o high speed input complement k18 in23p i/o high speed input k19 vtti power input termination supply k20 vtti power input termination supply l1 in08p i/o high speed input l2 in08n i/o high speed input complement l3 in07n i/o high speed input complement l4 in07p i/o high speed input l17 in24p i/o high speed input l18 in24n i/o high speed input complement l19 in25n i/o high speed input complement l20 in25p i/o high speed input m1 vcc power positive supply m2 vcc power positive supply m3 in09p i/o high speed input m4 in09n i/o high speed input complement m17 in26n i/o high speed input complement m18 in26p i/o high speed input m19 vcc power positive supply m20 vcc power positive supply n1 in11p i/o high speed input n2 in11n i/o high speed input complement n3 in10n i/o high speed input complement n4 in10p i/o high speed input n17 in27p i/o high speed input n18 in27n i/o high speed input complement n19 in28n i/o high speed input complement n20 in28p i/o high speed input p1 vtti power input termination supply ball mnemonic type description p2 vtti power input termination supply p3 in12p i/o high speed input p4 in12n i/o high speed input complement p17 in29n i/o high speed input complement p18 in29p i/o high speed input p19 vtti power input termination supply p20 vtti power input termination supply r1 in14p i/o high speed input r2 in14n i/o high speed input complement r3 in13n i/o high speed input complement r4 in13p i/o high speed input r17 in30p i/o high speed input r18 in30n i/o high speed input complement r19 in31n i/o high speed input complement r20 in31p i/o high speed input t1 vtti power input termination supply t2 vtti power input termination supply t3 in15p i/o high speed input t4 in15n i/o high speed input complement t17 in32n i/o high speed input complement t18 in32p i/o high speed input t19 vtti power input termination supply t20 vtti power input termination supply u1 vcc power positive supply u2 vcc power positive supply u3 in16n i/o high speed input complement u4 in16p i/o high speed input u5 out17n i/o high speed output complement u6 out18p i/o high speed output u7 out20n i/o high speed output complement u8 out21p i/o high speed output u9 out23n i/o high speed output complement u10 out24p i/o high speed output u11 out26n i/o high speed output complement u12 out27p i/o high speed output u13 out29n i/o high speed output u14 out30p i/o high speed output u15 out32n i/o high speed output complement u16 out33p i/o high speed output u17 in33p i/o high speed input u18 in33n i/o high speed input complement u19 vcc power positive supply u20 vcc power positive supply v1 vee power negative supply v2 vee power negative supply v3 vee power negative supply v4 vee power negative supply v5 out17p i/o high speed output v6 out18n i/o high speed output complement v7 out20p i/o high speed output v8 out21n i/o high speed output complement ball grid descriptions (continued)
rev. a AD8152 ? ball mnemonic type description v9 out23p i/o high speed output v10 out24n i/o high speed output complement v11 out26p i/o high speed output v12 out27n i/o high speed output complement v13 out29p i/o high speed output v14 out30n i/o high speed output complement v15 out32p i/o high speed output v16 out33n i/o high speed output complement v17 vee power negative supply v18 vee power negative supply v19 vee power negative supply v20 vee power negative supply w1 vee power negative supply w2 vee power negative supply w3 vee power negative supply w4 vcc power positive supply w5 vtto power output termination supply w6 out19n i/o high speed output complement w7 vtto power output termination supply w8 out22n i/o high speed output complement w9 vtto power output termination supply w10 out25n i/o high speed output complement w11 vcc power positive supply w12 out28n i/o high speed output complement w13 vtto power output termination supply w14 out31n i/o high speed output complement ball mnemonic type description w15 vtto power output termination supply w16 vcc power positive supply w17 vee power negative supply w18 vee power negative supply w19 vee power negative supply w20 vee power negative supply y1 vee power negative supply y2 vee power negative supply y3 vee power negative supply y4 vcc power positive supply y5 vtto power output termination supply y6 out19p i/o high speed output y7 vtto power output termination supply y8 out22p i/o high speed output y9 vtto power output termination supply y10 out25p i/o high speed output y11 vcc power positive supply y12 out28p i/o high speed output y13 vtto power output termination supply y14 out31p i/o high speed output y15 vtto power output termination supply y16 vcc power positive supply y17 vee power negative supply y18 vee power negative supply y19 vee power negative supply y20 vee power negative supply ball grid descriptions (continued)
rev. a ? AD8152?ypical performance characteristics 80ps/div 100mv/div tpc 1. eye pattern 3.2 gbps 100mv/div 20ps/div peak-peak jitter = 35ps std dev = 5.1ps tpc 2. jitter @ 3.2 gbps 100mv/div 1.2ns/div tpc 3. response, 3.2 gbps, 32-bit pattern 1111 1111 0000 0000 1010 1010 1100 1100 100mv/div 200ps/div tpc 4. eye pattern 1.5 gbps 100mv/div 20 p s/div peak-peak jitter = 35ps std dev = 5.2ps tpc 5. jitter @ 1.5 gbps 100mv/div 2.5ns/div tpc 6. response, 1.5 gbps, 32-bit pattern 1111 1111 0000 0000 1010 1010 1100 1100 ( 2.5 v supply, vcc = vtti = vtto, data rate = 3.2 gbps; prbs 2 23 ?; differential output swing = 800 mv p-p; r l = 50 ; input amplitude = 0.4 v p-p single-ended; unless otherwise noted.)
rev. a AD8152 ? duty cycle distortion ?ps 1400 800 0 ?0 30 frequency 020 1200 1000 600 400 40 50 bin width = 5ps 200 ?0 ?0 ?0 ?0 10 tpc 7. duty cycle distortion distribution data rate ?gbps 100 90 0 0.5 4.0 1.0 eye height ?% 1.5 2.0 2.5 3.0 3.5 80 70 60 50 40 30 20 10 v out @ data rate v out @ 0.5gbps 100 %eye height = tpc 8. eye height vs. data rate data rate ?gbps 50 4.0 1.0 jitter ?ps 1.5 2.0 2.5 3.0 3.5 45 40 35 30 25 15 10 5 0 peak-peak jitter standard deviation 20 tpc 9. jitter vs. data rate unit interval 1.e+00 0.1 ?.5 bit error rate ?.4 ?.3 ?.2 ?.1 0 0.2 0.3 0.4 0.5 1.e?1 1.e?2 1.e?3 1.e?4 1.e?5 1.e?6 1.e?7 1.e?8 1.e?9 1.e?0 1.e?1 1.e?2 tpc 10. bit error rate vs. unit interval 100mv/div 80ps/div peak-peak jitter = 35ps std dev = 5.6ps tpc 11. crosstalk, 3.2 gbps, attack signal off (see tpc 25) 100mv/div 80ps/div peak-peak jitter = 46ps std dev = 6.5ps tpc 12. crosstalk, 3.2 gbps, attack signal on (see tpc 25)
rev. a ?0 AD8152 temperature ? c 50 50 0 peak-peak jitter ?ps 10 20 30 40 45 40 35 30 25 60 70 80 90 55 3.2 gbps 1.5 gbps tpc 13. single point jitter vs. temperature input amplitude ?mv 0 jitter ?ps 10 100 1000 standard deviation peak?eak jitter 120 100 80 60 40 20 0 tpc 14. jitter vs. single-ended input amplitude input cml ? v 160 peak-peak jitter ?ps 140 120 100 80 60 180 40 20 3.8 3.2 2.9 2.6 2.3 2.0 1.7 1.4 1.1 0.8 0.5 3.5 input amplitude = 50mv p-p @3.3v @2.5v tpc 15. jitter vs. input common-mode level supply voltage ? v jitter ?ps 80 70 60 50 4.0 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 3.8 40 30 20 10 0 standard deviation peak-peak jitter tpc 16. jitter vs. supply v ol ? v peak-peak jitter ?ps ?.4 0 160 140 120 100 80 60 40 20 ?.2 ?.0 ?.6 ?.4 ?.2 0 i out = 16ma i out = 24ma i out = 32ma ?.8 tpc 17. jitter vs. v ol (relative to vcc) i out ?ma jitter ?ps 0 10 50 45 40 35 30 25 20 15 peak?eak jitter standard deviation 510152 0253035 5 0 tpc 18. jitter vs. programmed i out
rev. a AD8152 ?1 propagation delay ?ps frequency 600 0 160 140 120 100 80 60 40 20 bin width = 5ps 625 650 675 700 725 750 tpc 19. variation in propagation delay 740 780 760 800 660 720 700 680 640 620 600 propagation delay ?ps temperature ? c 40 30 20 10 05060708090 tpc 20. propagation delay vs. temperature supply voltage ?v 725 propagation delay ?ps 700 675 650 625 600 750 2.8 2.6 2.4 2.2 2.0 3.0 3.2 3.4 3.6 3.8 tpc 21. propagation delay vs. supply i out code i out ?ma meas ured ideal 012345678 9 0 2 4 6 8 10 11 12 13 14 15 16 10 12 14 16 18 20 22 24 26 28 32 30 34 tpc 22. i out vs. i out code
rev. a ?2 AD8152 AD8152 in##p out##p in##n out##n vee = ?.5v i out = 16ma, v out hi = 0v, v out lo = ?.4v v in amplitude = 400mv p-p single-ended, v in hi = ?.2v prbs 2 23 ?1 pa ttern generator vcc vtto vtti 50 50 data out data out trigger out trigger in high speed sampling oscilloscope ?db ?db ?db ?db tpc 23. negative supply test circuit i out = 16ma, v out hi = 2.5v, v out lo = 2.1v v in amplitude = 400mv p-p single-ended, v in hi = 2.7v prbs 2 23 ?1, inputs and outputs are ac-coupled pa ttern generator vcc vtto 2.5v v tti 50 50 data out data out trigger out trigger in high speed sampling oscilloscope ?db ?db vee ?db ?db AD8152 in##p out##p in##n out##n 0.1 f 0.1 f 0.1 f 0.1 f tpc 24. positive supply test circuit a ttack signal applied to in25. in25 broadcast to all outputs except out27. tw o separate pattern generators used to provide input pattern to AD8152. ou tputs not connected to oscilloscope are terminated with external 50 to gnd. 50 50 ?db ?db ?db ?db AD8152 vee = ?.5v pa ttern generator #2 data out data out vcc vtto vtti trigger out trigger in high speed sampling oscilloscope in24n in24p out27p out27n in25n in25p out00p...out26p out28p...out33p out00n...out26n out28n...out33n 50 50 ?db ?db pa ttern generator #1 at ta ck signal data out data out tpc 25. crosstalk test circuit
rev. a AD8152 ?3 table i. address and data buses connection/current bit output address pins data pins a6 a5 a4 a3 a2 a1 a0 d5 d4 d3 d2 d1 d0 0 = connection latches 1 = output current level msb lsb msb lsb table ii. connection data and address programming examples connection/ data pins current bit output address pins (used to select inputs) comments 0 = connection msb lsb msb lsb a6 a5 a4 a3 a2 a1 a0 d5 d4 d3 d2 d1 d0 0 000000 000000 program in00 to out00 0 000000 100001 program in33 to out00 0 100001 011111 program in31 to out33 0 111111 000000 b roadcast in00 to all outputs 0 000000 111111 d isable out00 0 100001 111111 d isable out33 0 111111 111111 d isable all outputs (broadcast) table iii. output-current level data and address programming examples connection/ data pins current bit output address pins (used to select inputs) comments 1 = current level msb lsb msb lsb a6 a5 a4 a3 a2 a1 a0 d5 d4 d3 d2 d1 d0 10 0 000 0x x0 000 program out00 to current?ode 00 (2 ma) 10 0 000 0x x1 111 program out00 to current?ode 15 (32 ma) 11 0 000 1x x0 111 program out33 to current?ode 07 (16 ma) 11 1 111 1x x1 000 broadcast current?ode 08 to all outputs (18 ma) table iv. basic control strobe functions reset cs we re upd function 0x xx xg lobal reset. disables all outputs and resets all output current to code 0111 (16 ma). 11 xx x disable all control signals. signal matrix/currents remain the same. d5:d0 are high impedance. 10 01 xw rite enable. write d5:d0 data into first rank register addressed by a6:a0. 10 x0 x single-output readback. second rank register data for output a6:a0 appears on d5:d0. 10xx0 g lobal update. copy all first rank data into second rank registers. 10 01 0 transparent write and update. d5:d0 immediately control programming. use re as gating signal.
rev. a ?4 AD8152 cs we a[6:0]inputs d[5:0]inputs t csw t asw t wp t dsw t ahw t ahw t chw t dhw figure 3a. first rank write cycle table v. first rank write cycle symbol parameter conditions min typ max unit t csw setup time chip select to write enable t a = 25 c0 ns t asw address to write enable 0 ns t dsw data to write enable vcc = 3.3 v 1 ns t chw hold time chip select from write enable 0 ns t ahw address from write enable 0 ns t dhw data from write enable 0 ns t wp width of write enable pulse 10 ns cs update enabling out[0:33][n:p] outputs t oggle out[0:33][n:p] outputs da ta from rank 1 t csu t uoe t uw t chu disabling out[0:33][n:p] outputs t uod da ta from rank 1 da ta from rank 2 previous rank 2 data t uot figure 3b. second rank update cycle table vi. second rank update cycle symbol parameter conditions min typ max unit t csu setup time chip select to update t a = 25 c0 ns t chu hold time chip select from update 0 ns t uoe output enable times update to output enable vcc = 3.3 v 25 45 ns t uot output toggle times update to output reprogram 25 45 ns t uod output disable times update to output disabled 25 45 ns t uw width of update pulse 10 ns
rev. a AD8152 ?5 cs update input {data 1} we enabling out[0:33][n:p] outputs disabling out[0:33][n:p] outputs input {data 1} input {data 0} t csu t uot t uoe t uw t wot t wod t whu t chu input {data 2} figure 4a. transparent write and update cycle table vii. transparent update cycle symbol parameter conditions min typ max unit t csu setup time chip select to update t a = 25 c0 ns t chu hold time chip select from update vcc = 3.3 v 0 ns t uoe output enable times update to output enable 35 50 ns t woe * write enable to output enable 35 50 ns t uot output toggle times update to output reprogram 25 45 ns t wot write enable to output reprogram 25 45 ns t uod * output disable times update to output disabled 25 45 ns t wod write enable to output disabled 25 45 ns t whu setup time write enable to update 0 ns t uw width of update pulse 10 ns * not shown cs re input d[5:0] a[5:0] outputs addr 1 addr 2 { addr 1} data da ta {addr 2} t aa t rde t csr t rha t chr t rdd figure 4b. second rank readback cycle table viii. second rank readback cycle symbol parameter conditions min typ max unit t csr setup time chip select to read enable t a = 25 c0 ns t chr hold time chip select from read enable vcc = 3.3 v 0 ns t rha address from read enable 5 ns t rde enable time data from read enable 15 ns t aa access time data from address 15 30 ns
rev. a ?6 AD8152 reset disabling out[0:33][n:p] outputs t tod t tw figure 5. asynchronous reset table ix. asynchronous reset symbol parameter conditions min typ max unit t tod disable time output disable from reset t a = 25 c102 5ns t tw width of reset pulse vcc = 3.3 v 10 ns control interface the AD8152 control interface receives and stores the desired connection matrix and output levels for the 34 input and 34 output signal pairs. the interface consists of 34 rows of double-rank 6-bit latches, one for each output. the 6-bit data-word stored in these latches indicates to which (if any) of the 34 inputs the output will be connected, as well as the full-scale output current. one output at a time can be preprogrammed by addressing the output and writing the desired connection data or output cur- rent into the first rank of latches. this process can be repeated until each of the desired output changes has been preprogrammed. all output connections can then be programmed at once by passing the data from the first rank of latches into the second rank. the output connections always reflect the data programmed into the second rank of latches and do not change until the first rank of data is passed into the second rank. if necessary for system verification, the data in the second rank of latches can be read back from the control interface. at any time, a reset pulse can be applied to the control interface to globally reset the appropriate second rank data bits, disabling all 34 signal output pairs and resetting the output currents. to facili tate multiple chip address decoding, there is a chip select pin. all logic signals except the reset pulse are ignored unless the chip select pin is active. the chip select pin disables only the control logic inter face and does not change the operation of the signal matrix. the chip select pin does not power down any of the latches, so any data programmed in the latches is preserved. all control pins are level-sensitive, not edge-triggered. control pin description a[6:0] inputs output address pins. the binary encoded address applied to the lower a[5:0] input pins determines which of the 34 outputs is being programmed (or being read back). the most significant bit, a6, determines whether the data pins contain information for the connection register bank or the output level register bank. using the broadcast address, a[5:0] = ?11111?will simulta- neously program data into all outputs at once. d[5:0] inputs/outputs input configuration or output level data pins. in write mode, when the bank selection bit a6 is low, the binary encoded data applied to pins d[5:0] determine which of the 34 inputs is to be connected to the output specified with the a[5:0] pins. the most significant bit is d5, and the least significant bit is d0. to disable an output completely, the input address d[5:0] = ?11111 should be written into the input configuration bank at the desired output address. in write mode, when the bank selection bit a6 is high, the binary encoded data applied to pins d[3:0] indicate the output current level to be used for the output specified with the a[5:0] pins. the reset default is ?111?for 16 ma. each lsb is 2 ma. in readback mode, pins d[5:0] are low impedance outputs indicating the data-word stored in the second rank for the out- put specified with the a[5:0] pins and the bank specified with the a6 bit. the readback drivers were designed to drive high impedances only, so external drivers connected to the d[5:0] should be disabled during readback mode. we input first rank write enable. forcing this pin to logic low allows the data on pins d[5:0] to be stored in the first rank latch for the output specified by pins a[6:0]. the we pin must be returned to a logic high state after a write cycle to avoid overwriting the first rank data. update input second rank write enable. forcing this pin to logic low allows the data stored in all 34 first rank latches (in both banks) to be trans- ferred to the second rank latches. the signal connection matrix will be reprogrammed when the second rank data and levels are changed. this is a global pin, transferring all 34 rows of data at once. it is not necessary to program the address pins. it should be noted that after initial power-up of the device, the first rank data is undefined. it is desirable to preprogram all 17 outputs before performing the first update cycle. re input second rank read enable. forcing this pin to logic low enables the output drivers on the bidirectional d[5:0] pins, entering the read- back m ode of operation. by selecting an output address with the a[6:0] pins and forcing re to logic low, the 6-bit data stored in the second rank latch for that output address will be written to d[5:0] pins. data should not be written to the d[5:0] pins externally while in readback mode. the re is a higher priority pin than the we pin, so first rank programming is not possible while in readback mode.
rev. a AD8152 ?7 cs input chip select. this pin must be forced to logic low to program or receive data from the logic interface, with the exception of the reset pin, described below. this pin has no effect on the sign al pairs and does not alter any of the stored control data. reset input global output disable pin. forcing the reset pin to logic low will disable all outputs, setting both ranks of all 34 input connec- tion latches, regardless of the state of any other pins. this has the effect of immediately disabling the 34 output signal pairs in the matrix. the output level information is also changed. it is necessary to momentarily hold reset at a logic low state when powering up the AD8152 in order to avoid random internal contention where multiple inputs may be connected to one output. the reset pin is not gated by the state of the chip select pin, cs . control interface levels the AD8152 control interface shares the data path supply pins, vcc and vee. the potential between the positive logic supply vcc and the negative supply vee must be at least 2.25 v and no more than 3.63 v. regardless of supply, the logic threshold is approximately one-half the supply range, allowing the interface to be used with most lvcmos and lvttl logic drivers. output addressing the AD8152 is programmed using a memory interface module, with parallel address and data buses. six bits (a5:a0) are used to address the outputs. by setting the decimal value of these address bits to a value from 0 to 33 inclusive, then one of the 34 outputs is uniquely addressed. one additional code, 63 (all 1s), is used for the broadcast mode. if this address is selected, then all outputs will receive the same programming. the remaining addresses in the space are not valid and are reserved, codes 34 to 66 inclusive. (see table i.) connection and output current programming a seventh address bit (a6) determines which of two types of programming is selected. if a6 = 0, connection matrix program- ming is selected. if a6 = 1, output current programming is selected. using the data bus once it is determined which output is to be programmed (or broad- cast to all outputs) and which type of programming (connection/ output-current), then the data bits (d5:d0) further define the programming action. if the selection is connection programming (a6 = 0), then the data bits select the input that is to be connected to the addressed output. if the broadcast address is selected, then the data bits select the input that will be connected to all 34 outputs. (see table ii.) a disable code (d5:d0 = 63, or all 1s) is used to disable (and power down) the particular output that is addressed. a broadcast disable can be effected by setting code 63 on both the address bus and the data bus along with a6 = 0. output-current programming a current source in each output can be digitally programmed to any one of 16 different current levels. changing these current levels will change the amplitude of the output swing that is developed across the internal 50 w termination resistors. to program the current for a particular output, its address is set on a5:a0 (00?3), while a6 is set to 1. the four lsbs of the data address (d3:d0) are then used to select one of the 16 output current levels. d4 and d5 are ?on? cares?for output current programming. (see table iii.) if it is desired to program all outputs to the same current level, then the broadcast code 63 can be placed on the address bus (a5:a0), along with a6 = 1. (d3:d0) will then program all output currents to the same level. when the current code is set to 0000, a minimum current level of 2 ma is obtained. for any other code, the current can be calculated by (current code) 2 ma + 2 ma. refer to table iii. for example, 16 ma can be programmed by code 0111. this is 7 2 ma + 2 ma = 16 ma. register-control signals several single-ended logic input pins control the register loading associated with the address and data buses described in the previ- ous section. the control functions are tabulated in table iv. there are dual ranks of registers for the data that programs the AD8152. the first rank registers accumulate the data for the various outputs as they are being programmed one by one. the second rank registers actually control the functions of the device. the reset signal is used to reset the connection matrix, disable all outputs, and set all of the output currents to a default condition at code 0111. this action sets the output current to a nominal value of 16 ma. the data in the first rank latches is also reset by the assertion of reset . the cs signal is used to enable the control interface. if several devices are used in a system with the other control signals bussed, the cs signal can be used to select an individual device to change its programming. the we signal is used to enable writing data to the first rank registers. this data will not immediately affect the features of the AD8152. the update signal transfers the data from the first rank registers to the second rank registers. after assertion of update , the data actively controls the AD8152 functions. the second rank registers can be read back through the data bus. the output is addressed on a5:a0 and the connection/current is selected via a6. asserting re will cause the second rank data to appear on the data bus. the re function will dominate over we if both are asserted at the same time. broadcast readback is not permitted. some typical programming waveforms for the control signals are provided in figure 6. va lid address input va l i d data input va lid address input va l i d data input a[6:0 ] d[5:0 ] we update figure 6. programming waveforms input/output coupling the AD8152 has internal 50 w termination resistors for each single-ended input and output. this can also provide a 100 w termination for a 100 w differential transmission line. all of the input termination resistors connect to one common point called vtti. similarly, each of the output termination resistors connects to one common point called vtto. the voltage can be set independently at vtti and vtto to accommodate various interface architectures.
rev. a ?8 AD8152 input coupling one way to simplify the input circuit and make it compatible with a wide variety of driving devices is to use ac coupling. this has the effect of isolating the dc common-mode levels of the driver and the AD8152 input circuitry. for example, the xaui inter- connect specification for 10 gbps ethernet requires ac coupling in order to ensure that there are no interactions of dc levels between the transmitting and receiving devices. ac coupling requires that the signal patterns have no long-term dc component, which may occur in any random data stream. codes such as 8b/10b, called for in the xaui specification, are used in many data communications systems to ensure that the data pattern is benign in an ac-coupled link. this is accomplished by run-length limiting (rll), which sets a maximum for the number of 1s or 0s that can occur consecutively. in addition, residual dc components are monitored and modified by keeping track of the running disparity, excess of 1s versus 0s or vice versa. for the AD8152 inputs, ac coupling requires a capacitor in series with each single-ended input signal, as shown in figure 7. this should be done in a manner that does not interfere with the high speed signal integrity of the pc board. the details of this are covered in the section on board layout guidelines. the two critical variables are setting the proper voltage for vtti and selecting the correct value of coupling capacitors. 50 vtti vcc 50 vee inxxp inxxn c inp c inn figure 7. ac-coupling input signal from AD8152 on the AD8152 side of the input coupling capacitor, the average value of the single-ended input voltage will be at the voltage set at vtti. the range of allowable voltages is a function of the accept- able input voltages of the active circuitry of the AD8152 inputs and the amplitude of the input signal. the operating input range of the AD8152 extends from vcc + 0.2 v to 0.8 v above vee. the total range that will be occupied by the input signal will be its average value (as established by the voltage applied to vtti) plus or minus one half the single-ended swing of the signal. for a standard 800 mv p-p differential signal, the single-ended swing is 400 mv p-p. thus, the signal will swing 200 mv about the average value equal to vtti. if vtti is set equal to vcc, then the single-ended signal will just meet the specifications where its highest excursion will be 0.2 v higher than vcc. the lowest level to set vtti is 0.8 v above vee. this will cause the negative signal excursions to stay within the operating range. with ac-coupled inputs, there is no power consumption advan- tage associated with varying vtti. as a practical matter, it might be desirable to set vtti at the same voltage as vtto so that only one supply is necessary. refer to the vtto section for more information. output coupling each single-ended output of the AD8152 has a termination resistor that ties to a common point called vtto. w hen vtto is varied, it will change the common-mode levels of the outputs and the power dissipation of the output stages when they are enabled. the individual output currents are programmable. varying this current will change the lower level of the output voltage (and thus the peak-to-peak swing) and also change the power dissipation in the output stages. to obtain a standard 800 mv p-p differential output (single-ended = 400 mv p-p), the output current should be programmed to 16 ma. with an effective termination resis- tance of 25 w , this will generate the proper differential voltage. if the AD8152 drives another device that is ac-coupled, there is no interaction of the dc levels on each side of the coupling capacitors (see figure 8). the dc levels for the AD8152 can be calculated independent of the levels of the device that is driven. the upper allowable setting for vtto is 0.2 v higher than vcc. the signals will be pulled up to this level at their highest excursion. however at this setting, the power dissipation will be a maximum. to save power, vtto can be lowered. the lowest level for vtto will be determined by the lowest output level allowable (v ol ) by the AD8152 output when it is logically low. the output at any time should not go lower than 1.0 v below vcc. if the single-ended swing of an output is 400 mv p-p, then the lowest that vtto can go is 0.6 v below vcc. for more information on v ol , see tpc 17. vtto vee i = 2ma (code) + 2ma 50 50 outxxp outxxn AD8152 vee vcc vtt vcc driven device vee figure 8. ac-coupling output signal from AD8152
rev. a AD8152 ?9 is powered down. thus, the total number of active inputs will affect the total power consumption. the core of the device performs the crosspoint switching function. it draws a fixed quiescent current whenever the AD8152 is powered from vcc to vee. an output predriver section draws a current that is proportional to the programmed output current, i out . this current always flows from vcc to vee. it is treated separately from the output current, which flows from vtto, and might not be the same voltage as vcc. the final section is the outputs. for an individual output, the programmed output current will flow through two separate paths. one is the on-chip termination resistor, and the other is the transmission line and the destination termination resistor. the nominal parallel impedance of these two paths is 25 w . the sum input te rminations inpu ts out- puts v tti vee vcc vtto vtt 50 50 inp inn 50 50 i out outp outn 50 50 ou tput terminations v ol = v tto ?(i out 25 ) d riven device te rminations o ptional coupling capacitors s witch mat rix ou tput pre- driver i = 32ma i = .25 i out 50 i out 2 p = p = (v indiffrms ) 2 100 (v ol ) (i out ) p = i = 2ma per acti ve input figure 9. power consumption block diagram table x. power consumption output input output switch + termination input output termination current total resistors stage core predriver resistors source power quiescent current 32 ma current per active channel v in / (r termination ) 2 ma 0.25 i out 0.5 i out i out current per active channel for differential v in = 800 mv p-p sine 566 mv rms/100 v out = 800 mv p-p = 5.66 ma 2 ma 4 ma 4 ma 8 ma 16 ma 2.5 v operation ( vcc ?vee = 2.5 v , vtto = 2.5 v, i out = 16 ma) per channel power 3.2 mw 5 mw 10 mw 8 mw 33.6 mw power for all channels active 108.8 mw 170 mw 80 mw 340 mw 272 mw 1.03 w 2.0 w percentage of total power 5% 8% 4% 17% 13.6% 51% 3.3 v operation ( vcc vee = 3.3 v, vtto = 3.3 v, i out = 16 ma) per channel power 3.2 mw 6.6 mw 13.2 mw 8 mw 46.4 mw power for all channels active 108.8 mw 224 mw 106 mw 449 mw 272 mw 1.47 w 2.63 w percentage of total power 4% 9% 4% 17% 10% 56% AD8152 power consumption there are several sections of the AD8152 that draw varying power depending on the supply voltages, the type of i/o coupling used, and the status of the AD8152 operation. figure 9 shows a block diagram of these sections. these are described briefly below and then in detail later in the data sheet. table x summarizes the power consumption of each section and is a useful guide as the following sections are reviewed. the first section is the input termination resistors. the power dissi pated in the termination resistors is the result of their being driven by the respective driving stage. also, there might be dc power dissipated in the input termination resistors if the inputs are dc - coupled and the driving source reference is a dc voltage that is not equal to vtti. in the next section, the active part of the input stages, each input is powered only when it is selected. if an input is not selected, it
rev. a ?0 AD8152 of these two currents will flow through the switches and the cur rent source of the AD8152 output circuit and out through vee. the power dissipated in the transmission line and the destination resistor will not be dissipated in the AD8152, but will have to be supplied from the power supply, and is a factor in the overall system power. the current in the on-chip termination resistors and the output current source will dissipate power in the AD8152 itself. input termination resistors the power dissipated in the input termination resistors is delivered by the driving source. first, assume the driving wave- for m for an individual input is a differential square wave with an ampli tude of v inpp. then the power dissipated in this input is (vinpp) 2 /2rterm. however, this result is quite pessimistic, because at high fre- quencies, the wave shape is usually more sinusoidal than square. if instead, a differential sine wave of amplitude vinpp is assumed, then its rms amplitude is 0.7 times that of a square w ave. this will yield a power that is one half of the square wave case. the assumed wave shape is not too critical because the fraction of the power dissipated in the input termination resistors is not very large. a further effect is that the input signal might travel over a path that attenuates the signal. this will usually be a function of frequency. thus, for such a case, some of the signal power will be dissipated in the signal path. this will reduce the amount of power dissipated in the AD8152 input terminations. if dc coupling is used, a dc current will flow from vtti through the termination resistors if the dc voltage of the drive circuit is not equal to vtti. the additional power in each input termination resistor will be the current that flows multiplied by the 50 w value of the input terminations. for a point of reference, assume a channel has a sinusoidal input of 800 mv p-p differential. the power dissipated for a single input will be 3.2 mw. if all 34 input channels are driven the same, then the power in the input terminations will be 109 mw. input stage the input stages are powered down when not in use. there is about 2 ma that flows through an enabled input from vcc to vee. thus, the power dissipated by an enabled input is 5 mw for a supply of 2.5 v and 6.6 mw for a 3.3 v supply. for all 34 inputs enabled, the respective figures are 170 mw for a 2.5 v supply and 224 mw for a 3.3 v supply. switch matrix the switch matrix draws a fixed 32 ma when the AD8152 is powered. this current flows from vcc to vee. the power dissi- pation from this current is 80 mw at 2.5 v and 106 mw at 3.3 v. output predrivers the output predrivers draw additional current when each of the outputs is enabled. this extra current is proportional to the programmed output current. the extra predriver current for a channel will be 25 percent of the programmed output current for that channel. this current will also flow from vcc to vee. when an output is enabled and programmed to 16 ma, an addi- tional 4 ma will flow in the predriver section. this will dissipate 10 mw at 2.5 v or 13.2 mw at 3.3 v for an individual output. for all 34 outputs enabled and programmed to 16 ma, the predriver power will be 340 mw at 2.5 v or 449 mw at 3.3 v. outputs the output current is forced by a current source that is pro- grammed to a variable amount of current from 2 ma to 32 ma in 2 ma steps. for the two logic switch states, this current flows through an on-chip termination resistor and a parallel path to the destination device and its termination resistor. the power in this parallel path is not dissipated by the AD8152. the nominal programmed output current is 16 ma. with the two parallel 50 w resistors at each collector (25 w equivalent), this current will create a 400 mv p-p swing in each half of the circuit. the differential output voltage will be 800 mv p-p. under steady state conditions and with a data pattern that is run-length limited so that its low frequency content is signifi cantly higher than the rc pole formed by the coupling capacitor and the termination resistors, the common-mode level at the AD8152 outputs will be 400 mv lower than vtto. each output will then swing 200 mv from this level, which is a 400 mv p-p single- ended output swing. at the high level, there will be 200 mv across the termination resistor. this will dissipate a power of 0.8 mw. at the low level, the 600 mv across the termination resistor will dissipate a power of 7.2 mw. since the output signal is basically 50% duty cycle, the average power dissipated will be the average of these two values or 4 mw. by symmetry, the other differential output will dissi pate the same power. this yields an on-chip termination-resistor power dissipation of 8 mw per channel for each output, or 272 mw for all 34 outputs. the full output current (from both on- and off-chip termination resistors) will flow in the lower part of each output. this current flows only in the side that is ?n,?or in its low state (v ol ). this voltage is 600 mv below the dc level at vtto. thus, for vtto = 2.5 v, v ol = 1.9 v, and the power dissipa- tion for i out = 16 ma is 30.4 ma. for all 34 channels, the power is 1.03 w. if vtto = 3.3 v, then v ol = 2.7 v. the single power is 43.2 mw and the power for all 34 channels is 1.47 w. if vtto = 2.5 v, then the additional power is given by 16 ma [(2.5 v ?(16 ma 25 w )] = 33.6 mw. thus, the total AD8152 power dissipation for this output is 37.6 mw. if all 34 outputs are enabled with the same i out , the total power dissipation is 1.28 w. thus it can be seen that the outputs are the major contributor to the power dissipation. power saving considerations while the AD8152 power consumption is very low compared to similar devices, careful control of its operating conditions can yield further power savings. significant power reduction can be realized by operating the part at a lower voltage. compared to 3.3 v operation, a supply voltage of 2.5 v can result in power savings of about 25 percent. there is virtually no performance penalty when operating at lower voltage. a second measure is to disable outputs when they are not being used. this can be done on a static basis if the output is not used, or on a dynamic basis if the output does not have a constant stream of traffic. since the majority of the power dissipated is in the output stage, some of its flexibility can be used to lower the power consump tion.
rev. a AD8152 ?1 first, the output current can be programmed to the smallest amount required to maintain ber performance. if an output circuit always has a short length and the receiver has good sensitivity, then a lower output current can be used. it is also possible to lower the voltage on vtto to lower the power dissipation. the amount that vtto can be lowered is dependent on the lowest of all the output? v ol . this will be determined by the output that is operating at the highest pro- grammed output current since v ol = vtto ?(i out 25 w ). evaluation board and pcb layout hints the AD8152 evaluation board was designed to allow the user to analyze signal integrity in many configurations, as controlled by a standard pc. the fr4 board comes equipped with a full complement of 136 sma connectors to support the complete 34 34 matrix of points. each differential pair of microstrip is connected to either top mount or side-launch sma connectors. the mounting area of the short center pin top-mount sma connectors are drilled (seven holes) and stubbed for greatly improved performance. in the area surrounding sma top-mount center pin and drill holes, all internal planes are relieved or cleared out (see figure 10 for layout). all top-mount smas sit on pcb top level top view of top level trace microstrip sma center pin plane relief drill holes (7 each) bottom view of bottom level trace figure 10. top-mount sma pcb layout, two views the fr4 pc board is eight layers with a thickness of 62 mils (1.57 mm). the two outer most metal layers hold the high speed microstrip routing lines. the two outer most dielectric layers are 5 mils thick and must be controlled impedance (50 w ) layers. these are the only two layers that require controlled impedance. the next two i nner metal layers are ground (reference) planes for the microstrip and are the shell for the sma connectors. the re main- ing four inner metal layers are for the four AD8152 supply and digital control signal routing. from top to bottom the four supply layers are vtto, vcc, vee, and vtti. because all four supply pcb metal layers float, positive, negative, and even dual-supply configurations are possible. the variety of supply configurations ease the connection of test equipment. the four inner supply layers also provide an interlayer capacitance, which has better impedance versus frequency than standard chip capacitors. dielectric thickness silkscreen copper layer number 1. 1.50/ top microstrip width = 8.0mils 2. 0.50/gnd 3. 0.50/vtto 4. 0.50/vcc 5. 0.50/vee 6. 0.50/vtti 7. 0.50/gnd 8. 1.50/bottom microstrip width = 8.0mils 0.5mils 5.0mils 4.0mils 16.0mils 4.0mils 16.0mils 4.0mils 5.0mils 0.5mils silkscreen thickness/designation (in ounces) figure 11. evaluation board stack-up
rev. a ?2 AD8152 the variety of supply configurations cause the need for a supply agile digital control circuitry. this is done by a programmable logic device (pld), which provides instructions to the AD8152. the pld supply is typically tied with jumpers across the AD8152? vcc and vee supplies (jumpers j3 and j4). the pld is addressed from the pc by way of digital isolators. these couplers isolate pc levels from the pld and allow for any level shifting. if desired, the user can drive the pld supply separately as long as the vee of the AD8152 and the pld are tied together (remove jumper j3 and leave j4 installed). this allows one to measure the AD8152 only supply current, for example. board construction or stack-up figure 11 is a picture of AD8152 evaluation board stack-up from top to bottom. the layer stack-up has been made symmetrical to avoid board warpage during manufacture. the microstrip layout and dimensions are shown in figure 12. the microstrip trace width was chosen to be 8 mils. this allows relative ease in routing through the bga rows that are 50 mils (1.27 mm) apart. the outer two out of four rows of high speed signals are routed on top of the pcb, while the inner two rows are via holed to the board? opposite side and then routed outward. wider microstrip is desirable for reducing eye height loss versus long traces; how- ever, the routing will be more difficult as the AD8152 is approached. the wide microstrip would have to be necked down in width in order to be routed into the bga. the necking will increase trace impedance and therefore induce more signal reflection problems. microstrip traces bga corner outline via hole (gray) chip capacitor (805) size figure 13. bga corner capacitor layout figure 12. cross-sectional layout and dimensioning (to scale) of differential during the layout of the differential microstrip, a software tool snaps the distance between the two traces to be a constant. if the distance is not kept constant, impedance variations will result. these fluctuations can be measured by time domain reflectometry (tdr). extra added inductance figure 14. poor capacitor layout bypass capacitor layout the AD8152 8-layer pcb takes advantage of buried interlayer capacitance. the vee to vcc planes are placed in the very middle of the board to make the highest value capacitor. the 4 mil (0.102 mm) dielectric spacing between vcc/vee yields 26 nf of capacitance. each AD8152 supply pin is directly connected to its supply plane through a via hole beneath the bga ball. the via hole size for a bga supply pin is slightly bigger than a signal via. this is to reduce the inductance of the connection, and it also happens to be a compact layout. for the chip capacitors, the via holes are placed directly in the middle of the mounting area and made as large as possible, i.e., greater than or equal to 35 mils (0.89 mm). this is to minimize inductance as much as possible. by minimizing inductance, the performance of the capacitor or impedance versus frequency response is not greatly diminished. note that chip capacitors will work up to only about 300 mhz. figure 14 is an example of a bypass capacitor layout that should be avoided in any high speed printed circuit board. this layout connects the chip capacitor mounting pads to small via holes through a skinny pcb trace. this amounts to four extra induc tors added to the capacitor, two largely from the skinny surface traces and two from small via holes. inductance is also variable with copper thickness and attachment method to power plane. thermal relief for soldering purposes also adds unwanted inductance and should be avoided.
rev. a AD8152 ?3 ecl driver to 50 scope inputs vcc vtto vtti = ?v vee = ?.5v AD8152 pp nn in out figure 15. evaluation board ecl driver test setup connections for testing the AD8152 evaluation board can be used under a variety of posi- tive or negative supply configurations. negative supply configurations, as shown in figure 15, allow the easiest hookup to test equip- ment because inputs and outputs can be direct coupled. in a real world application however, the negative supply configuration would be difficult because control logic levels must be shifted negative. figure 16 is an example of a loop-through test setup using a posi- tive supply. in this case, the test signal goes through the AD8152 twice. it is possible to loop through multiple times if desired, but jitter will increase with number of loop-throughs. the first i nput from the generator and the last output to a scope must be ac-coupled. however, an AD8152 output driving its own input can be direct-coupled. direct coupling to the first AD8152 input is not effective since generators usually want to see 50 w to ground. this would require vtti to be attached to ground, causing excessive power to be dissipated in the internal 50 w input ter mination resistors. secondly, when the AD8152 output tries to drive its own input with vtti = 0 v and vtto = 2.5 v, the input will pull the output stage levels down enough to shut off any signal toggling. all ac coupling shown is actually done with a set of bias tees. if desired, the bias tee can be used to monitor average dc voltage levels at an input or output (depending on direction installed), and it can also serve to change input dc levels. make sure the bias tees used in the setup have enough low frequency bandwidth to pass long patterns and keep edge rates intact. t he longer the pattern, the more low frequency bandwidth is needed. if ac coupling is desired on a user board, 0402 or 0603 sized capacitors can be installed on microstrip lines. the biggest 0402 size, xr7 type usable is 0.01 m f, which will work fine for short patterns (prbs 2 7 ?) and data rates down to 1.0 gbps. for long patterns a 0603 sized, xr7 type, 0.1 m f should be used. to decrease capacitive loading from the mounting area, clear out planes underneath the coupling capacitor. in figure 16, 6 db attenuators are placed before the AD8152 input ac-coupling or bias tees. this is because many generators won? go below 500 mv single-ended. the output pair of 6 db attenuators is present to protect the scope inputs and allow for higher scale voltages per division. the eye diagram is usually viewed differentially by using a simple p ?n math function. cabling used in this setup must be matched. mismatched cables cause either a p or n signal to be falsely delayed. this delay can show up as a change in the crossing point, from 50 percent in the eye diagram. to accurately check cable matches, a tdr setup is recommended. pa ttern generator vcc vtto 2.5v AD8152 p p n n in01 out01 v tti p n p n in02 out02 vee 50 50 data out data out trigger out trigger in high speed sampling oscilloscope ?db ?db ?db ?db vcc = vtti = vtto = 2.5v, vee = 0v, i out set = 16ma rti (referred to input) a mplitude = 400mv single?nded, v in hi = 2.7v (in01), prbs 2 23 ?, v oh = 2.5v, v ol = 2.1v, ac-coupled is from bias tees, programming: in01 to out02, in02 to out01. figure 16. positive supply loop-through test setup
rev. a ?4 AD8152 evaluation board control software the AD8152 evaluation board can be controlled by using a pc and a custom software program. the hardware interface uses a pc parallel (or printer) port. a standard printer cable is used to connect from the pc db-25 connector to the centronics-type connector on the evaluation board. figure 17 shows an evaluation board control panel from a pc display. a single screen allows control of all the programmable functions of the AD8152. the programming modes are listed in the mode box. select either i/o programming or current programming by selecting the appropriate radio button. these will allow either programming the switch matrix or the output currents one at a time. an alternative is to use the broadcast mode. this will either simultaneously program all of the outputs to one selected input or program all outputs to the same current. figure 17. evaluation board control panel in the i/o programming mode (nonbroadcast), the desired input is selected from the input select box by double-clicking on the appropriate input channel number. this will cause the same channel to appear in the active input selection indicator window. next, select the desired output from the output select box by double- clicking the appropriate output channel number. finally, the program button is clicked and the data is immedi ately sent to the evaluation board for programming the part to the selected i/o combination. if an additional output(s) is desired to be programmed to the same input, double-click the desired output channel number and click the program button. the programmed output table indicates which outputs are programmed to the input that is indicated in the active input selection window. if it is desired to disable an individual output, its radio button in the programmed output table can be clicked, and it will change from black to white to indicate that it is not enabled. note: it is not possible to program outputs by selecting their radio buttons. to observe the set of outputs that are connected to any input, double-click the desired input channel number from the input s elect box. the selected channel number will show up in the active i nput selection window and the programmed outputs will have a black dot in their radio button in the programmed output table. to program an output current, select the current programming button in the mode box. then double-click the desired output channel number from the output select table. next double-click the desired entry for the output current. finally, click the program button. if the broadcast button is selected from the mode box, all outputs will be treated the same. if i/o programming is selected, double- click the input channel number from the input select table a nd click the program button. this will cause all outputs to be programmed to the selected output, and all of the buttons will have a black dot in the programmed output table. for broadcast current p rogramming, double-click the desired output current. then click the program button. all of the outputs will be programmed to the selected output current. the r eset button will disable all outputs. in addition, all output currents will be programmed to the nominal value of 16 ma.
rev. a AD8152 ?5 figure 18. evaluation board top side signals
rev. a ?6 AD8152 figure 19. evaluation board bottom side signals, view from top
rev. a AD8152 ?7 figure 20. evaluation board vcc layer, view from top
rev. a ?8 AD8152 figure 21. evaluation board vee layer, view from top
rev. a AD8152 ?9 figure 22. evaluation board vtti layer, view from top
rev. a ?0 AD8152 figure 23. evaluation board vtto layer, view from top
rev. a AD8152 ?1 outline dimensions 256-ball grid array [sbga] (bp-256) dimensions shown in millimeters a b c d e f g h j k l m n p r t u v w y 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 a1 corner 27.00 bsc 24.13 ref 1.27 bottom 0.20 min seating plane 0.25 min 0.90 0.75 0.60 top 1.27 0.70 0.60 0.50 1.00 0.80 0.60 0.20 coplanarity seating plane ba ll diameter 24.13 ref 27.00 bsc a1 compliant to jedec standards mo-192-bal-2
c02984??/03(a) printed in u.s.a. ?2 rev. a AD8152 revision history location page 1/03?ata sheet changed from rev. 0 to rev. a. edits to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

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